Modeling and Characterization of Inconsistent Behavior of Gate Leakage Current with Threshold Voltage for Nano MOSFETs
American Journal of Modern Physics
Volume 7, Issue 4, July 2018, Pages: 166-172
Received: Jul. 13, 2018;
Accepted: Aug. 19, 2018;
Published: Sep. 15, 2018
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Yashu Swami, Department of Electronics & Communication Engineering, Motilal Nehru National Institute of Technology Allahabad, Allahabad, India
Sanjeev Rai, Department of Electronics & Communication Engineering, Motilal Nehru National Institute of Technology Allahabad, Allahabad, India
A strange relationship of gate leakage current and threshold voltage variation for nano MOSFETs is analyzed using factual strategy and subsequently a physical model is proffered. The gate leakage current increments with the threshold voltage before it diminishes at higher threshold voltage in nanoscale devices. This inconsistent behavior of gate leakage current with threshold voltage variations is precisely clarified in the manuscript through the concept of accord between two contrary operations: threshold voltage roll-off impact and gate leakage current reliance on surface potential. The tunneling gate leakage current density diminishes with threshold voltage over surface potential. However, the threshold voltage roll-off impact causes higher threshold voltage for larger channel length devices. The net gate leakage current is adjusted by these two contrary functions of threshold voltage. In addition, the rate of accretion of the gate leakage current with threshold voltage variation is also analyzed. The impact of the increase in the power supply voltage on the rate of accretion of the gate leakage current vs. threshold voltage curve is also explored. Thorough methodical TCAD simulations are accomplished to validate the proffered models. Both the experimental outcomes, TCAD simulations and physics based models are implemented to uncover and clarify the threshold voltage gate leakage relationship, particularly for nano MOSFETs. The proposed notion is not currently captured in conventional gate leakage nano device models, hence the proffered physical models may be utilized in progression of reliable and trustworthy TCAD simulation tools for nano devices.
Modeling and Characterization of Inconsistent Behavior of Gate Leakage Current with Threshold Voltage for Nano MOSFETs, American Journal of Modern Physics.
Vol. 7, No. 4,
2018, pp. 166-172.
Copyright © 2018 Authors retain the copyright of this article.
This article is an open access article distributed under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0/
) which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Roy, Gareth, et al. "Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs." IEEE Transactions on Electron Devices 53.12 (2006): 3063-3070.
Wang, Xingsheng, et al. "Statistical threshold-voltage variabiliy in scaled decananometer bulk HKMG MOSFETs: A full-scale 3-D simulation scaling study." IEEE Transactions on Electron Devices 58.8 (2011): 2293-2301.
Swami, Yashu, and Sanjeev Rai. "Modeling, Simulation, and Analysis of Novel Threshold Voltage Definition for Nano-MOSFET." Journal of Nanotechnology 2017 (2017).
Lundstrom, Mark, and Zhibin Ren. "Essential physics of carrier transport in nanoscale MOSFETs." IEEE Transactions on Electron Devices 49.1 (2002): 133-141.
Chang, Leland, et al. "Practical strategies for power-efficient computing technologies." Proceedings of the IEEE 98.2 (2010): 215-236.
Kanj, Rouwaida, et al. "Design considerations for PD/SOI SRAM: Impact of gate leakage and threshold voltage variation." IEEE Transactions on Semiconductor Manufacturing 21.1 (2008): 33-40.
Liu, Zihong, et al. "An anomalous correlation between gate leakage current and threshold voltage fluctuation in advanced MOSFETs." Electron Devices Meeting (IEDM), 2010 IEEE International. IEEE, 2010.
Swami, Yashu, and Sanjeev Rai. "Modeling and analysis of sub-surface leakage current in nano-MOSFET under cutoff regime." Superlattices and Microstructures 102 (2017): 259-272.
De Gyvez, J. Pineda, and Hans P. Tuinhout. "Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits." IEEE Journal of Solid-State Circuits 39.1 (2004): 157-168.
Koh, Meishoku, et al. "Limit of gate oxide thickness scaling in MOSFETs due to apparent threshold voltage fluctuation induced by tunnel leakage current." IEEE Transactions on Electron Devices 48.2 (2001): 259-264.
Iyer, Subramanian S., and Edward J. Nowak. "45 nm SOI and beyond-getting to a general purpose technology." SOI Conference, 2007 IEEE International. IEEE, 2007.
Narasimha, S., et al. "High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography." Electron Devices Meeting, 2006. IEDM'06. International. IEEE, 2006.
Swami, Yashu, and Sanjeev Rai. "Comparative methodical assessment of established MOSFET threshold voltage extraction methods at 10-nm technology node." Circuits and Systems 7.13 (2016): 32.
Swami, Yashu, and Sanjeev Rai. "Proposing an enhanced approach of threshold voltage extraction for nano MOSFET." Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2017 IEEE Asia Pacific Conference on. IEEE, 2017.
Lee, Wen-Chin, and Chenming Hu. "Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction-and valence-band electron and hole tunneling." IEEE Transactions on Electron Devices 48.7 (2001): 1366-1373.
Taur, Yuan, and Tak H. Ning. Fundamentals of modern VLSI devices. Cambridge university press, 2013.